1. Field of the Invention
The present invention generally relates to analogue-to-digital converting apparatus and, more particularly, to an analogue-to-digital converter suitable for processing an audio signal.
2. Description of the Prior Art
16-bit digital signal processors are generally utilized in the professional digital signal processing in the prior art. This type of 16-bit digital signal processor is not necessarily sufficient as a professional digital audio processor from a resolution and dynamic range standpoint. For this reason, digital processors of larger bit size, such as 18-bit to 20-bit digital signal processors, have been requested in order to provide higher resolution and wider dynamic range.
Recently, 18-bit to 20-bit professional analogue-to-digital converting apparatus have become commercially available in order to meet the above demand.
FIG. 1 shows an example of such prior-art analogue-to-digital converter apparatus. As shown in FIG. 1, this kind of known analogue-to-digital converter apparatus comprises an analogue-to-digital (A/D) converting circuit (so-called front end) 10 which employs a so-called .DELTA.-.SIGMA. modulation and a digital filter (so-called decimate filter circuit) 20 that converts data of high rate into data of low rate. The front end 10 and the decimate filter circuit 20 are respectively formed of LSIs (large scale integrated circuits).
The front end 10 of FIG. 1 includes, for example, four integrators 11 to 14 connected in series as shown in FIG. 2, and an analogue audio signal SA is supplied through an adder 15 to the integrator 11 of the first stage. An output of the integrator 14 of the final stage is fed through an A/D converter 16, a unit delay circuit 17 and a digital-to-analogue (D/A) converter 18 back to the adder 15, and the unit delay circuit 17 provides output data of, for example, 4 bits.
In the front end 10, the analogue audio signal SA is oversampled at a sampling rate N.multidot.fs (e.g., N=128) which is remarkably higher than a sampling rate fs (e.g., 48 kHz) required in the Nyquist chart and then quantized.
Frequency characteristics of the integrators 11 to 14 are set properly and the noise shaping is carried out, so that a noise within the audio signal band is reduced remarkably as shown in FIG. 3.
The decimate filter circuit 20 of FIG. 1 includes, for example, three moving average filters 21 to 23 connected in series, and an output of the moving average filter 23 of the last stage is supplied to a data extracting circuit 24. This data extracting circuit 24 is connected with an FIR (finite impulse response) type half-band filter 25 as shown in FIG. 4.
As shown in FIG. 4, the moving average filter 21 comprises an adder 21a, a subtractor 21b, a unit delay circuit 21d (simply represented by D in FIG. 4] and a shift register 21r having 64 taps.
Input data is commonly supplied to the adder 21a and the shift register 21r and the subtractor 21b subtracts an output of the shift register 21r from an output supplied thereto through the unit delay circuit 21d from the adder 21a. An output of the subtractor 21b is supplied to the adder 21a and an output of the adder 21a is supplied to the circuit of the next stage. The moving average filters 22 and 23 are constructed in a similar fashion.
The moving average filter 21 of the first stage moves and averages 6-bit data of high rate N.multidot.fs by an average length 64 to generate 12-bit data of the same rate. The moving average filters 22 and 23 of the next and final stages expand data length by 6 bits each by a similar moving and averaging process and the moving average filter 23 of the final stage derives 24-bit data of rate N.multidot.fs.
An over-all frequency characteristic of the moving average filters 21 to 23 is illustrated in FIG. 5.
The data extracting circuit 24 extracts 24-bit data from the output of the moving average filter 23 of the final stage at a rate of 2.multidot.fs and omits the lower 4 bits, whereby 20-bit data is supplied to the FIR filter 25 at a rate of 2.multidot.fs.
The FIR filter 25 attenuates a component exceeding the audio signal band to thereby generate 20-bit data at a predetermined low rate fs.
In the conventional analogue-to-digital converter apparatus described above, the front end 10 outputs the 4-bit data and the decimate filter circuit 20 is supplied with 6-bit data. Therefore, the output data and input data of the front end 10 and the decimate filter circuit 20, respectively, are not matched.
As a result, by only connecting the output of the front end 10 to the input of the decimate filter circuit 20, the dynamic range of 20 bits, for example, cannot be fully and effectively utilized from LSB (least significant bit) to MSB (most significant bit) in the output of the decimate filter circuit 20. There is then the problem that the performance of such apparatus cannot be demonstrated sufficiently.
More specifically, as shown in FIG. 1, 4 bit outputs of the front end 10 are respectively supplied to the upper 4 bits of the 6 bit inputs of the decimate filter circuit 20, while fixed "1", "0" are respectively supplied to the lower 2 bits of the 6-bit inputs. Thus, the output of the front end 10 is expanded to 6 bits and a DC offset in the output of the decimate filter circuit 20 is reduced.
If the analogue audio signal SA of sufficient level is input to the front end 10 in this state, then the output data thereof is fully and effectively utilized in a range of from "0000" to "1111". When the fixed lower 2 bits "1" and "0" are respectively added to the output data of the front end 10 the 6 bit inputs to the decimate filter circuit 20 are utilized from "000010" to "111110". As a consequence, 20 bit outputs of the decimate filter circuit 20 are represented from "00152" to "FFF57" in a hexadecimal notation with the result that the data is not fully and effectively utilized in a range of the above 16 bits.
As earlier noted, a 16-bit digital processor is generally utilized in the conventional professional audio signal processing. However, when the output of the front end 10 is saturated in the analogue-to-digital converter apparatus shown in FIG. 1, then the output of the decimate filter circuit 20 is not fully and effectively utilized from LSB to MSB. As a consequence, even in the 16-bit digital processor, an overload display function is not operated and there is then the risk that the quality of a reproduced sound is deteriorated.
In order to solve the aforesaid problem fundamentally, it is sufficient to develop a new 6-bit output front end or a new 4-bit input decimate filter circuit. The development of such front end and decimate filter circuit would be costly and time consuming.
In an attempt to solve the aforesaid problem by the use of an external circuit, it has been proposed to employ a digital signal processor (DSP) to amplify the output data of the decimate filter circuit such that 20 bits can be fully and effectively utilized from LSB to MSB.
However, the required DSP involves a large circuit and is very expensive. Also, there is then the problem that re-quantization noise occurs in accordance with the rounding processing in the calculation.
Further, a bit shift adding method is known, in which as shown by a dashed line in FIG. 1 a bit shifter circuit 31 and an adder 32 are employed to process the output data of the decimate filter circuit 20 by bit shift down processing and the processed data is added to the original data, whereby the output data of the decimate filter circuit 20 is amplified such that 20 bits data can be fully and effectively utilized from LSB to MSB.
However, although the bit shift adding method employs a simple circuit and is inexpensive, data of a lower bit is disturbed by data of a higher bit so that a clear reproduced sound cannot be obtained from the listener's standpoint, and the quality of the reproduced sound is deteriorated.
When 4-bit data is processed by the 2-bit shift down processing and added to the original data, then a jump of 2LSB level occurs regularly as shown by * * on the following table 1. In the table 1, OF represents an overflow of data.
______________________________________ input data shift data output data ______________________________________ H L H H L 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 1 1 0 0 * 0 0 1 1 0 1 0 0 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 0 1 1 1 0 1 1 1 0 1 * 1 0 0 0 1 0 0 0 1 0 * 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 0 1 0 1 1 0 0 1 0 1 1 1 0 * 1 1 0 1 1 1 0 0 1 1 * 1 1 1 1 1 1 0 1 1 1 OF1 1 0 0 1 1 1 0 1 1 OF1 1 0 1 1 1 1 1 1 1 OF1 1 1 1 ______________________________________